Integrated circuits (chips) comprise active transistors and passive components. The chips are designed and fabricated according to conventional design parameters and semiconductor process technologies that determine operating parameters and limits for the constituent transistors. Operating power is supplied to each transistor from one or more external power supplies such that each transistor is responsive to a specified power supply voltage that is below a maximum supply voltage limit for the transistor. To accommodate different transistor designs and their associated operating limits, the chip provides multiple power supply voltages, with each transistor connected to the appropriate supply voltage for safe and reliable operation.
As is known, a transistor comprises at least two pn junctions through which current flows to achieve transistor action. A MOSFET (metal-oxide semiconductor field effect transistor) comprises doped source and drain regions formed in a well of the opposite doping type. A region of the well between the source and drain is referred to as a channel. A conductive gate overlies the channel and is separated therefrom by a dielectric layer. Application of a voltage to the gate inverts the conductivity of the channel permitting current to flow between the source and the drain.
The equation for current flow for both an n-channel (NMOS) and a p-channel (PMOS) MOSFET is:I=K(W/L)(Vgs−Vt)(Vgs−Vt),where: K is a constant for a given technology, Vgs is the voltage between the gate and the source, Vt is the threshold voltage (the Vgs at which current starts to flow through the channel) and W/L is a width/length ratio of the MOSFET structure. The quantity (Vgs−Vt) is commonly known as Veff.
Application of an excessive voltage to a pn junction (such as the source/well of a MOSFET) can cause the junction to fail or break down, possibly resulting in transistor failure. Thus a maximum junction breakdown voltage is an important MOSFET operating limit.
Transistors designed to operate with different supply voltages may exhibit different breakdown limits, as there is a direct relationship between the transistor's nominal supply voltage and its junction breakdown characteristics. Transistors designed for operation at higher supply voltages generally exhibit higher breakdown voltages. Transistors can be operated near the maximum permitted supply voltage to increase operational speed in the case of a digital circuit and to provide maximum voltage headroom in an analog circuit.
Supplying a MOSFET with a voltage in excess of a breakdown voltage can shorten the transistor's life and cause performance limiting effects, all apparently related to an excessive electric field intensity within the transistor. The electric fields of interest include vertical and lateral fields within the transistor structure and fields across transistor junctions. Three known deleterious effects associated with high intensity electric fields are described below.
An excessive electric field across the gate dielectric causes current flow through the dielectric, possibly leading to dielectric breakdown. Also, in the case of a reverse biased pn junction, when the electric field across the junction is sufficient to cause either Zener or avalanche junction breakdown, excessive reverse current will flow, possibly leading to the generation of excess heat in the transistors or components with which it operates.
A MOSFET having a relatively high source-drain voltage creates a relatively large electric field intensity that accelerates the carriers through the channel from source to drain. If such a field is present while the MOSFET is operating in saturation (i.e., a high current flow from source to drain) the carriers may attain a sufficiently high energy such that upon collision with the channel silicon lattice atoms a fraction of the carriers are deflected into the gate dielectric (e.g., silicon dioxide). These high-energy carriers, referred to as “hot” carriers, degrade the quality of the gate dielectric, leading to premature failure of the transistor.
Continued operation of a transistor that is subject to one or more of these breakdown conditions will likely shorten the transistor's life and alter its performance over time.
Generally, there are three known approaches for overcoming the effects of an excessive electric field intensity within a MOSFET. One solution fabricates multiple MOSFET's on the chip, with each MOSFET having a different gate oxide thickness. Selection of the operative MOSFET for a specific circuit is based on the gate oxide thickness required to withstand the effects of the electric field generated by the circuit. While this technique provides a MOSFET capable of withstanding breakdown effects, fabrication process costs are increased by the extra masks and extra processing steps required, and an area penalty is incurred due to the increased chip area required to fabricate the multiple MOSFETS.
An extended-drain MOSFET includes an integrated resistor in series with the MOSFET drain. When a high current flows from the drain to the source, the voltage drop across the integrated resistor reduces the voltage at the drain and thus the magnitude of the source-drain electric field intensity. Generally, the simultaneous occurrence of a high source-drain voltage and a high drain current occurs only under transient operations. Thus, the only significant detrimental effect of the drain resistor is a slight reduction in response time, but the extended-drain MOSFET introduces an area penalty due to the area required by the integrated resistor.
A third solution uses a controllable protection circuit that prevents the application of excessive voltages to the MOSFET terminals. Within the protection circuit, voltages across transistor terminals are limited to values below breakdown.
A transistor's output voltage is related to its supply voltage, i.e., a first transistor operating at a first supply voltage provides a higher output voltage than a second transistor operating at a second supply voltage lower than the first supply voltage. In a circuit configuration where the first transistor output is supplied as an input to the second transistor, care must be exercised to ensure that the input does not exceed a breakdown voltage of the second transistor. For example, in a circuit where a signal is communicated between a first chip operating at 3.3 V and a second chip operating at 2.5 V, an input interface that can tolerate a 3.3 V input signal is disposed between the two chips to reduce the input voltage seen by the second chip, thereby limiting the breakdown effects on transistors and other components within the second chip.
One circuit configuration in which multiple transistors share a common output terminal is referred to as a “net.” In the net, multiple output drivers (i.e., transistors) drive (i.e., supply an input signal) to a network of components. At a given time, one of the output drivers drives the net while the others are in an off condition. Since all output drivers may not operate at the same power supply voltage, under certain operating conditions one or more of the off-state output drivers may be exposed to an excessive voltage, which can develop an excessive electric field in the transistor and possibly cause junction breakdown.